# Create the work library
#vlib work
#vmap work path 

# WORK HOME
set WORK_HOME D:/Document/Code/Python/image-filtering/rtl
set SIGNED_MULTI_HOME D:/Document/Code/Verilog/ErrorModel_acmulti8/TCAS2/signed
set UNSIGNED_MULTI_HOME D:/Document/Code/Verilog/ErrorModel_acmulti8/TCAS2/unsigned

# top module name
set TOP_MODULE sobel_edge_detect

# Compile the system verilog files

#vlog  $WORK_HOME/image_sharpen/*  
vlog $WORK_HOME/sobel_edge_detect/* 

# compile approximate multi
vlog $SIGNED_MULTI_HOME/apmulti8_41_1.1.1.1/*.v



# Run simulation
vsim -l sim.log -novopt work.$TOP_MODULE 

# Add wave
#    view wave
#    add wave -h *



# Run time
run -all



